1. Field of the Invention
The present invention relates to a Liquid-Crystal Display (LCD) panel having a pair of transparent substrates and a Liquid-Crystal (LC) layer. sandwiched between the pair of substrates, in which driving elements such as Thin-Film Transistors (TFTs) and Metal-Insulator-Metal (MIM) elements are arranged regularly on one of the pair of substrates, and an LCD device formed by using the panel. More particularly, the present invention relates to an LCD panel and an LCD device of the active-matrix addressing type that are applicable to compact, light-weight display devices with a comparative wide display area and that are capable of displaying images in different modes or aspects of resolution, which are typically used for electronic equipment, such as various portable or non-portable display terminals.
2. Description of the Prior Art
FIGS. 1 and 2 schematically show the configuration and operation of a prior-art LCD device of this sort, respectively.
The prior-art LCD device of FIG. 1 has a TFT panel 120 including a plurality of LC cells 105 arranged in a matrix array having m rows and U columns, a drain driver 107 for driving the panel 120, and a gaze driver 108 for driving the same, where m and n are positive integers greater than unity. The first to m-th rows of the matrix extend along the X axis in FIG. 1 and arranged along the Y direction in FIG. 1 at equal intervals. The first to n-th columns of the matrix extend along the Y axis and arranged along the X direction at equal intervals.
A TFT 102 is formed in each of the plurality of LC cells 105. Each cell 105 serves as a capacitor along with a display electrode (not shown) and a common electrode (not shown). Thus, the cell 105 is illustrated in FIG. 1 by a symbol of a capacitor. Each cell 105 corresponds to a pixel of the LCD device.
While the display electrodes are formed on the inner surface of a transparent glass substrate 101 along with the TFTs 102, the common electrodes are formed on the inner surface of another transparent glass substrate (not shown) that is coupled with the substrate 101 to be opposed thereto. Needless to say, a LC layer is formed in the space between the substrate 101 and the opposing substrate.
On the inner surface of the substrate 101, first to m-th gate lines 128-1, 128-2, . . . , and 128-m, first to n-th drain lines 127-1, 127-2, . . . , and 127-n, and the TFTs 102 are formed. The m gate lines 128-1 to 128-m extend respectively along the m rows of the matrix. The n drain lines 127-1 to 127-n extend respectively along the n columns of the matrix. The TFPTs 102 are located at the respective intersections of the gate lines 128-1 to 128-m and the drain lines 127-1 to 127-n. Thus, the total number of the TFTs 102 is equal to (mxc3x97n).
The gate lines 128-1 to 128-m, which are parallel to each other, are electrically connected to the gate driver 108 located outside the substrate 101. The drain lines 127-1 to 127-n, which are parallel to each other and perpendicular to the gate lines 128-1 to 128-m, are electrically connected to the drain driver 107 located outside the substrate 101.
Each of the n drain lines 127-1 to 127-n is electrically connected to the drain electrodes D of the TFTs 102 that are aligned along the corresponding drain line 127-1, 127-2, . . . , or 127-n (i.e., the corresponding column of the matrix). Each of the m gate lines 128-1 to 128-m is electrically connected to the gate electrodes G of the TFTs 102 that are aligned along the corresponding gate line 128-1, 128-2, . . . , or 128-m (i.e., the corresponding row of the matrix).
The source S of each of the TFTs 102 is electrically connected to one of the two electrodes forming the corresponding LC cell 105 (i.e., the corresponding display electrode) formed on the substrate 101. The other electrodes of the cells 105 (i.e., the common electrode) are electrically connected to a common voltage source, such as the ground.
The gate driver 108 is applied with a vertical start signal VSP0 and a vertically-shifting clock signal VCK0. In response to the signals VSP0 and VCK0, the gate driver 108 generates selection signals VG1, VG2, . . . , and VGm to select a corresponding one of the rows of the matrix and then, supplies them to the corresponding gate lines 128-1, 128-2, . . . , and 128-m, respectively.
The drain driver 107 is applied with an image signal DAT0, a horizontal start signal HSP0, a horizontally-shifting clock signal HCK0, and a latch signal LP0. In response to the signals DAT0, HSP0, HCK0, and LP0, the drain driver 107 generates pixel data signals HD1, HD2, . . . , and HDn to form images and then, supplies them to the corresponding drain lines 127-1 to 127-n, respectively The supply or input of the pixel data signals HD1 to HDn is controlled by the latch signal LP0.
The prior-art LCD device shown in FIG. 1 operates in the following way.
The application of the horizontal start signal HSP0 to the drain driver 107 triggers off the input of the image signal DAT0 for one of the m rows of the matrix into the driver 10?. The input of the image signal DAT0 is performed to be synchronized with the application of the horizontally-shifting clock signal HCK0. Based on the applied image signal DAT0, the drain driver 107 generates the pixel data signals HD1 to HDn for one of the m rows of the matrix and then, supplies them simultaneously to the drain lines 127-1 to 127-n with specific timing, respectively.
On the other hand, the application of the vertical start signal VSP0 to the gate driver 108 triggers off the generation of the selection signals VG1 to VGm. Then, the driver 108 sequentially supplies the selection signals VG1 to VGm to the gate lines 128-1 to 128-m, respectively. As shown in FIG. 2, each of the signals VG1 to VGm contains a pulse and therefore, the TFTs 102 applied with the signal VG1, VG2, . . . , or VGm at their gate electrodes are turned on. Through the TFTs 102 thus turned on, the drain lines 127-1 to 127-n are electrically connected to the corresponding LCD cells 105, thereby selecting the cells 105 arranged along one of the m rows of the matrix. Since the pulses of the signals VG1 to VGm are successively shifted in phase to each other, the cells 105 arranged along each of the first to m-th rows of the matrix are successively selected.
The pixel data signals HD1 to HDn are respectively supplied to the selected cells 105 located in the selected rows of the matrix and then, the pixel data contained in the signals HD1 to HDn are written thereinto. Thus, the cells 105 are driven by the signals HD1 to HDn, thereby displaying images on the screen of the prior-art LCD device corresponding to the pixel data thus written.
Typically, the selection signals VG1 to VGm have waveforms A1 to Am denoted by the solid lines in FIG. 2 at the input ends 128-1A to 128-mA of the gate lines 128-1 to 128-m, respectively. On the other hand, the signals VG1 to VGm have waveforms B1 to Bm denoted by the broken lines in FIG. 2 at the output ends 128-1B to 128-mB of the lines 128-1 to 128-m, respectively. It is seen from FIG. 2 that each of the waveforms Bl to Bm includes obtuse rising and falling edges at the output ends 128-1B to 128-mB. The obtuse rising and falling edges of the waveforms Bl to Bm will cause some temporal shift in or phase delay xcex94t0 of the waveforms Al to Am The shift or delay xcex94t0 has been known as the xe2x80x9cgate line delayxe2x80x9d, which is induced by the resistance of the lines 128-1 to 128-m and parasitic capacitances existing near the lines 128-1 to 128-m.
Accordingly, the supply timing of the pixel data signals HD1 to HDn needs to be properly adjusted while taking the xe2x80x9cgate line delayxe2x80x9d xcex94t0 into consideration. If not so, the pixel data contained in the signals HD1 to HDn are unable to be correctly written into all the corresponding LC cells 105.
For example, as shown in FIG. 2, it is supposed that the writing operation of the pixel data from the signals HD1 to HDn for the first row of the matrix into the corresponding cells 105 is started at the time TA1. At this time, the selection signal VG1 rises at the input end 128-1A of the gate line 128-1. Then, the writing operation of the pixel data in the signal HD1 to HDn for the second row of the matrix into the corresponding cells 105 is started at the time TA2. In this case, all the TFTs 102 connected to the gate line 128-1 are not turned off and consequently, there arises a problem that the pixel data contained in the signals HD1 to HDn for the second row are written into the corresponding cells 105 located in the first row.
To prevent this problem, in the prior-art LCD device shown in FIG. 1, the vertically-shifting clock signal VCK0 is supplied to the gate driver 108 so as to be forward-shifted in phase by a period xcex94t0xe2x80x2 with respect to the latch signal LP0, where the period xcex94t0xe2x80x3 is equal to the gate line delay xcex94t0. In other words, the gate line delay xcex94t0 is compensated by giving the time difference xcex94t0xe2x80x2 (=xcex94t0) between the signals VCK0 and LP0. Due to this compensation, the pixel data signals HD1 to HDn are supplied to the drain lines 127-1 to 127-n at the delayed times TB1 to TBm, respectively. As a result, the pixel data contained in the signals HD1 to HDn can be correctly written into all the cells 105.
The period or time difference xcex94t0xe2x80x2 between the signals VCK0 and LP0 is generated by a timing controller (not shown) that controls the drain driver 107 and the gate driver 108. The time difference xcex94t0xe2x80x2 is produced by counting the number of the pulses of the horizontally-shifting clock signal HCK0 up to a specific value.
In general, when LCD devices are designed to be applicable to several different modes or aspects of resolution (i.e., different numbers of the pixels to be used), the pulse length of the horizontally-shifting clock signal HCK0 needs to vary according to the selected mode or aspect of resolution. From the point of view, the number of the pulses of the signal HCK0 needs to have different values according to the required different pulse-lengths. Thus, there arises a problem that the configuration of the timing controller is complicated and the dimensions thereof is expanded.
Another prior-art LCD device of this sort is disclosed in the Japanese Non-Examined Patent Publication No. 63-261389 published in 1988. In this device, the writing operation of the pixel data into the LC cells is delayed with respect to the vertically-shifting clock signals by using an analog delay circuit provided outside the TFT panel.
In the prior-art LCD device disclosed in the Publication No. 63-261399, however, an integrator circuit formed by a resistor or resistors and a capacitor or capacitors and a Schmitt trigger amplifier are required to be provided outside the TFT panel. Thus, there is a problem that the configuration of the driver circuits of the TFT panel is complicated and the number of necessary electronic parts or components is difficult to be reduced.
Accordingly, an object of the present invention is to provide an LCD panel and an LCD device that make it possible to optimize the timing to write pixel data into LC cells without using any timing controller.
Another object of the present invention is to provide an LCD panel and an LCD device that simplify the configuration of driver circuits.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, an LCD panel is provided, which is comprised of
(a) a first plurality of signal lines extending along rows of a matrix and arranged along columns of the matrix;
(b) a second plurality of signal lines extending along the columns of the matrix and arranged along the rows of the matrix;
(c) LC cells arranged in an array of the matrix;
(d) driving elements for driving the respective LC cells; and
(e) a signal delay line for generating a temporal delay in a timing control signal;
the signal delay line extending along the rows of the matrix and formed not to be electrically connected to the driving elements;
the signal delay line having a first end into which the timing control signal is inputted and a second end from which the timing control signal containing the delay is outputted.
Each of the first plurality of signal lines is used for supplying a selection signal to the driving elements located in a corresponding one of the rows of the matrix. Each of the second plurality of signal lines is used for supplying a data signal to the driving elements located in a corresponding one of the columns of the matrix.
The timing control signal containing the delay is used for timing control of supplying the data signals to the driving elements located in the corresponding columns of the matrix through the second plurality of signal lines.
With the LCD panel according to the first aspect of the present invention, the signal delay line extending along the rows of the matrix (i.e., the first plurality of signal lines) is provided for generating the delay in the timing control signal. The timing control signal containing the delay, which is generated by the signal delay line, is used for timing control of supplying the data signals to the driving elements located in the corresponding columns of the matrix.
Since the signal delay line is intersected with the second plurality of signal lines in the same manner as that of the first plurality of signal lines, the amount of the delay of the timing control signal is approximately equal to that of the selection signals generated by the second plurality of signal lines. This means that the data signals are supplied to the driving elements at the optimized timing corresponding to the amount of the delay of the selection signals.
Moreover, even if the amount of the delay of the selection signals is changed by switching the mode or aspect of resolution, the amount of the delay of the timing control signal varies automatically according to the change in the amount of the delay of the selection signals.
As a consequence, the timing to write the image data into the LC cells can be optimized without using any timing controller even if the mode or resolution is changed.
Furthermore, since no complicated driving configuration are required, the configuration of the driver circuits can be simplified.
In a preferred embodiment of the panel according to the first aspect of the invention, the signal delay line has approximately the same electrical characteristic as that of the first plurality of signal lines. In this embodiment, there is an additional advantage that the temporal delay in the timing control signal is substantially or completely equal to that of the selection signals, which leads to complete compensation of the temporal delay in the selection signals.
The electrical characteristic of the signal delay line contains typically the electrical resistance and parasitic capacitance of the signal delay line. However, it may contain any other factors affecting the temporal delay in the timing control signal.
In another preferred embodiment of the panel according to the first aspect of the invention, the signal delay line is located on the input side of the data signals into the second plurality of signal lines. In this embodiment, there is an additional advantage that the amount of the temporal delay of the timing control signal can be substantially or completely equalized to that of the selection signals to be generated by the second plurality of signal lines. This is because the connection line of the signal delay line to a drain driver can be as short as possible.
In a still another preferred embodiment of the panel according to the first aspect of the invention, the driving elements are TFTs. Each of the first plurality of signal lines is electrically connected to gate electrodes of the TFTs located in a corresponding one of the rows of the matrix. each of the second plurality of signal lines is electrically connected to source or drain electrodes of the TFTs located in a corresponding one of the column of the matrix.
In a further preferred embodiment of the panel according to the first aspect of the invention, the timing control signals containing the delay at the second end of the signal delay line has a waveform with approximately the same obtuse rising and falling edges as those of each of the selection signals at corresponding rear ends of the second plurality of signal lines
Preferably, each of the first plurality of signal lines is approximately perpendicular to the second plurality of signal lines. It is preferred that the driving elements are TFTs, because TFTs are very popular and they provide high-quality images.
According to a second aspect of the present invention, an LCD device is provided, which is comprised of:
(a) an LCD panel including
(a-1) a first plurality of signal lines extending along rows of a matrix and arranged along columns of the matrix;
(a-2) a second plurality of signal lines extending along the columns of the matrix and arranged along the rows of the matrix:
(a-3) LC cells arranged in an array of the matrix; and
(a-4) driving elements for driving the respective LC cells; and
(a-5) a signal delay line for generating a temporal delay in a timing control signal;
the signal delay line extending along the rows of the matrix and formed not to be electrically connected to the driving elements;
the signal delay line having a first end into which the timing control signal is inputted and a second end from which the timing control signal containing the delay is outputted:
(b) a selection signal source for respectively supplying selection signals to the first plurality of signal lines; and
(c) a data signal source for respectively supplying data signals to the second plurality of signal lines.
Each of the selection signals is supplied from the selection signal source to the driving elements located in a corresponding one of the rows of the matrix through a corresponding one of the first plurality of signal lines.
Each of the data signals is supplied from the data signal source to the driving elements located in a corresponding one of the columns of the matrix through a corresponding one of the second plurality of signal lines
The timing control signal containing the delay is applied to the data signal source, thereby performing timing control of supplying the data signals to the driving elements located in the corresponding columns of the matrix through the second plurality of signal lines.
With the LCD device according to the second aspect of the present invention, the LCD panel according to the first aspect of the present invention is combined with the selection signal source and the data signal source. Thus, because of approximately the reason as that of the panel according to the first aspect, the timing to write the image data into the LC cells can be optimized without using any timing controller even if the mode of resolution is changed. Also, the configuration of the driver circuits can be simplified.
In a preferred embodiment of the device according to the second aspect of the invention, the signal delay line has approximately the same electrical characteristic as that of the first plurality of signal lines. In this embodiment, there is an additional advantage that the temporal delay in the timing control signal is substantially or completely equal to that of the selection signals, which leads to complete compensation of the temporal delay in the selection signals.
In another preferred embodiment of the device according to the second aspect of the invention, the signal delay line is located on the input side of the data signals into the second plurality of signal lines. In this embodiment, there is an additional advantage that the amount of the temporal delay of the timing control signal can be substantially or completely equalized to that of the selection signals to be generated by the second plurality of signal lines. This is because the connection line of the signal delay line to a drain driver can be as short as possible.
In a still another preferred embodiment of the device according to the second aspect of the invention, the driving elements are TFTs. Each of the first plurality of signal lines is electrically connected to gate electrodes of the TFTs located in a corresponding one of the rows of the matrix. Each of the second plurality of signal lines is electrically connected to source or drain electrodes of the TFTs located in a corresponding one of the column of the matrix. In this embodiment, there is an additional advantage that the advantages of the invention are realized conspicuously.
In a further preferred embodiment of the device according to the second aspect of the invention, the selection signals are respectively supplied to the first plurality of signal lines to be synchronized with the timing control signal that does not contain the delay.
In a still further preferred embodiment of the device according to the second aspect of the invention, the timing control signals containing the delay has a waveform with approximately the same obtuse rising and falling edges as those of each of the selection signals at corresponding rear ends of the second plurality of signal lines.